Explaining-Away Penalty on Quantum Hardware

Test 4 (IBM Heron) · Substrate: Real Quantum Hardware · Status: PASS · April 5, 2026

Question

Does the explaining-away penalty — the information cost of blending two signals on a single channel — exist on real quantum hardware? The Void Framework predicts I(D;M|Y) > 0 wherever probability distributions are blended, regardless of substrate. Čencov's uniqueness theorem guarantees this. But guarantees need empirical confirmation.

Why Quantum Hardware

Quantum error correction circuits provide the cleanest possible test environment. Every coordinate is controlled to machine precision:

No rubric. No subjective scoring. No cultural bias. Physics enforces the coordinates. If the penalty shows up here, it cannot be a measurement artifact.

What the Discrete Regime Tells Us

In saturated softmax channels (LLMs, quantum circuits with limited depth), the penalty doesn't grow monotonically — it peaks at moderate engagement then declines as output collapses toward determinism. The peak at depth 2 means the damage is concentrated in a critical window. For LLMs, this maps to the RLHF training window. For quantum circuits, it maps to the regime where error correction is most needed.

What This Rules Out

• The penalty is not an artifact of LLM architecture
• The penalty is not an artifact of the scoring rubric
• The penalty is not cultural or subjective
• The penalty is not substrate-specific
• No technology substitution (quantum AI, neuromorphic, biological) routes around it

Barrier Height

Test 5b measured the geodesic barrier height: approaches π/√2 ≈ 2.221 asymptotically as the system approaches the low-noise limit. This is a derived quantity (from the Fisher metric in geodesic coordinates), not a fitted parameter. The barrier is what separates two-point from three-point regimes on the manifold.

Code

All test scripts: ops/lab/qec-eckert-tsim/. Simulation mode (CPU) available via bloqade-tsim. Hardware results archived with timestamps and IBM job IDs.